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preliminary fm25h20 2-mbit (256 k 8) serial (spi) f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-85935 rev. *d revised january 24, 2014 2-mbit (256 k 8) serial (spi) f-ram features 2-mbit ferroelectric random a ccess memory (f-ram) logically organized as 256 k 8 ? high-endurance 100 trillion (10 14 ) read/writes ? 151-year data retention (see the data retention and endur- ance table) ? nodelay? writes ? advanced high-reliability ferroelectric process very fast serial peripheral interface (spi) ? up to 40-mhz frequency ? direct hardware replacement for serial flash and eeprom ? supports spi mode 0 (0, 0) and mode 3 (1, 1) sophisticated write protection scheme ? hardware protection using the write protect (wp ) pin ? software protection using write disable instruction ? software block protection for 1/4, 1/2, or entire array low power consumption ? 1 ma active current at 1 mhz ? 80 ? a (typ) standby current ? 3 ? a sleep mode current low-voltage operation: v dd = 2.7 v to 3.6 v industrial temperature ?40 ? c to +85 ? c packages ? 8-pin small outline integrated circuit (soic) package ? 8-pin thin dual flat no leads (tdfn) package restriction of hazardous substances (rohs) compliant functional overview the fm25h20 is a 2-mbit nonv olatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes similar to a ram. it provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by serial flash, eeprom, and other nonvolatile memories. unlike serial flash and eeprom, the fm25h20 performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product offers substantial write endurance compared with other nonvolatile memories. the fm25h20 is capable of supporting 10 14 read/write cycles, or 100 million times more write cycles than eeprom. these capabilities make the fm25h20 ideal for nonvolatile memory applications, requirin g frequent or rapid writes. examples range from data collecti on, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash or eeprom can cause data loss. the fm25h20 provides substantia l benefits to users of serial eeprom or flash as a hardwa re drop-in replacement. the fm25h20 uses the high-speed spi bus, which enhances the high-speed write capability of f-ram technology. the device specifications are guaranteed ov er an industrial temperature range of ?40 ? c to +85 ? c. logic block diagram instruction decoder clock generator control logic write protect instruction register address register counter 256 k x 8 f-ram array 18 data i/ o register 8 nonvolatile status register 3 wp cs hold sck so si not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 2 of 22 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 overview............................................................................ 4 memory architecture........................................................ 4 serial peripheral interface ? spi bus.............................. 4 spi overview............................................................... 4 spi modes................................................................... 5 power up to first access ........ .................................... 6 command structure .................................................... 6 wren - set write enable latch ............................ ..... 6 wrdi - reset write enable latch............................... 6 status register and write prot ection ............................. 7 rdsr - read status register. .................................... 8 wrsr - write status register .................................... 8 memory operation............................................................ 8 write operation ........................................................... 8 read operation ........................................................... 9 hold pin operation ................................................. 10 sleep mode ............................................................... 10 endurance ................................................................. 11 maximum ratings........................................................... 12 operating range............................................................. 12 dc electrical characteristics ........................................ 12 data retention and endurance ..................................... 13 capacitance .................................................................... 13 thermal resistance........................................................ 13 ac test conditions ........................................................ 13 ac switching characteristics ....................................... 14 power cycle timing ....................................................... 16 ordering information...................................................... 17 ordering code definitions ...... ................................... 17 package diagrams.......................................................... 18 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design supp ort............. .......... 22 products .................................................................... 22 psoc? solutions ...................................................... 22 cypress developer community................................. 22 technical support .................. ................................... 22 not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 3 of 22 pinouts figure 1. 8-pin soic pinout figure 2. 8-pin tdfn pinout pin definitions pin name i/o type description cs input chip select . this active low input activates the device. when high, the device enters low-power standby mode, ignores other inputs, and the output is tristated. when lo w, the device internally activates the sck signal. a falling edge on cs must occur before every opcode. sck input serial clock . all i/o activity is synchronized to the seri al clock. inputs are latched on the rising edge and outputs occur on the falling edge. because the device is synchronous, the clock frequency may be any value between 0 and 40 mhz and may be interrupted at any time. si [1] input serial input . all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet idd specifications. so [1] output serial output . this is the data output pin. it is driven during a read and remains tristated at all other times including when hold is low. data transitions are driven on the falling edge of the serial clock. wp input write protect . this active low pin prevents write operation to the status register when wpen is set to ?1?. this is critical because other writ e protection features are co ntrolled through the status register. a complete explanation of write protection is provided in ?status register and write protection? on page 7. this pin must be tied to v dd if not used. hold input hold pin . the hold pin is used when the host cpu must interrupt a memory operation for another task. when hold is low, the current operation is suspended. the device ignores any transition on sck or cs . all transitions on hold must occur while sck is low. this pin must be tied to v dd if not used. v ss power supply ground for the device. must be connected to the ground of the system. v dd power supply power supply input to the device. exposed pad no connect the exposed pad on the bottom of 8-pi n tdfn package is not connected to the die. the exposed pad should be left floating. hold sck 1 2 3 4 5 cs 8 7 6 v dd si so top view not to scale v ss wp so cs v ss wp si v dd sck hold 1 2 4 3 5 6 7 8 pad exposed top view not to scale note 1. si may be connected to so for a single pin data interface . not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 4 of 22 overview the fm25h20 is a serial f-ram memory. the memory array is logically organized as 262,144 8 bits and is accessed using an industry-standard serial peripheral interface (spi) bus. the functional operation of the f-ram is similar to serial flash and serial eeproms. the major di fference between the fm25h20 and a serial flash or eeprom with the same pinout is the f-ram's superior write performance, high endurance, and low power consumption. memory architecture when accessing the fm25h20, the user addresses 256k locations of eight data bits each. these eight data bits are shifted in or out serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an opcode, and a three-byte address. the upper 6 bits of the address range are 'don't care' values. the complete address of 18 bits specifies each byte address uniquely. most functions of the fm25h20 are either controlled by the spi interface or handled by on-board circuitry. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. th at is, the memory is read or written at the speed of the spi bus. unlike a serial flash or eeprom, it is not necessary to poll the device for a ready condition because writes occur at bus speed. by the time a new bus transaction can be shifted in to the device, a write operation is complete. this is explained in more detail in the interface section. serial peripheral interface ? spi bus the fm25h20 is a spi slave device and operates at speeds up to 40 mhz. this high-speed serial bus provides high-performance serial communication to a spi master. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm25h20 operates in spi mode 0 and 3. spi overview the spi is a four-pin inte rface with chip select (cs ), serial input (si), serial output (so), a nd serial clock (sck) pins. the spi is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. a device on the spi bus is activated using the cs pin. the relationship between chip select, clock, and data is dictated by the spi mode. this device supports spi modes 0 and 3. in both of these modes, data is clocked into the f-ram on the rising edge of sck starting from the first rising edge after cs goes active. the spi protocol is controlled by opcodes. these opcodes specify the commands from the bus master to the slave device. after cs is activated, the first byte transferred from the bus master is the opcode. followin g the opcode, any addresses and data are then transferred. the cs must go inactive after an operation is complete and before a new opcode can be issued. the commonly used terms in the spi protocol are as follows: spi master the spi master device controls the operations on a spi bus. an spi bus may have only one master with one or more slave devices. all the slaves share the same spi bus lines and the master may select any of t he slave devices using the cs pin. all of the operations must be initiated by the master activating a slave device by pulling the cs pin of the slave low. the master also generates the sck and all the data transmission on si and so lines are synchronize d with this clock. spi slave the spi slave device is activated by the master through the chip select line. a slave device gets the sck as an input from the spi master and all the communicat ion is synchronized with this clock. an spi slave never in itiates a communication on the spi bus and acts only on the instruction from the master. the fm25h20 operates as an spi slave and may share the spi bus with other spi slave devices. chip select (cs ) to select any slave device, the master needs to pull down the corresponding cs pin. any instruction can be issued to a slave device only while the cs pin is low. when the device is not selected, data through the si pin is ignored and the serial output pin (so) remains in a high-impedance state. note a new instruction must begin with the falling edge of cs . therefore, only one opcode can be issued for each active chip select cycle. serial clock (sck) the serial clock is generated by the spi master and the communication is synchronized with this clock after cs goes low. the fm25h20 enables spi modes 0 and 3 for data communication. in both of these modes, the inputs are latched by the slave device on the rising edge of sck and outputs are issued on the falling edge. therefor e, the first rising edge of sck signifies the arrival of the first bit (msb) of a spi instruction on the si pin. further, all data inputs and outputs are synchronized with sck. data transmission (si/so) the spi data bus consists of two lines, si and so, for serial data communication. si is also referred to as master out slave in (mosi) and so is referred to as master in slave out (miso). the master issues instructions to t he slave through the si pin, while the slave responds through the so pin. multiple slave devices may share the si and so lines as described earlier. the fm25h20 has two separate pins for si and so, which can be connected with the master as shown in figure 3 . not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 5 of 22 for a microcontroller that has no dedicated spi bus, a general-purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the hold and wp pins. figure 4 shows such a configuration, which uses only three pins. most significant bit (msb) the spi protocol requires that the first bit to be transmitted is the most significant bit (msb). this is valid for both address and data transmission. the 2-mbit serial f-ram requires a 3-byte address for any read or write operation. because the address is only 18 bits, the first six bits, which are fed in are ignored by the device. although these six bits are ?don?t care?, cypress recommends that these bits be set to 0s to enable seamless transition to higher memory densities. serial opcode after the slave device is selected with cs going low, the first byte received is treated as the opcode for the intended operation. fm25h20 uses the standard opcodes for memory accesses. invalid opcode if an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin until the next falling edge of cs , and the so pin remains tristated. status register fm25h20 has an 8-bit status register. the bits in the status register are used to configure the device. these bits are described in table 3 on page 7 . spi modes fm25h20 may be driven by a microcontroller with its spi peripheral running in either of the following two modes: spi mode 0 (cpol = 0, cpha = 0) spi mode 3 (cpol = 1, cpha = 1) for both these modes, the input data is latched in on the rising edge of sck starting from the first rising edge after cs goes active. if the clock starts from a high state (in mode 3), the first rising edge after the clock toggles is considered. the output data is available on the falling edge of sck. figure 3. system configuration with spi port cs1 cs2 hold1 hold2 fm25h20 fm25h20 wp1 wp2 sck si so sck si so cs hold wp cs hold wp sck mosi miso spi microcontroller figure 4. system configuration without spi port fm25h20 microcontroller sck si so cs hold wp p1.2 p1.1 p1.0 not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 6 of 22 the two spi modes are shown in figure 5 on page 6 and figure 6 on page 6 . the status of the clock when the bus master is not transferring data is: sck remains at 0 for mode 0 sck remains at 1 for mode 3 the device detects the spi mode fr om the status of the sck pin when the device is selected by bringing the cs pin low. if the sck pin is low when the device is selected, spi mode 0 is assumed and if the sck pin is high, it works in spi mode 3. power up to first access the fm25v20 is not accessible for a t pu time after power-up. users must comply with the timing parameter, t pu , which is the minimum time from v dd (min) to the first cs low. command structure there are seven commands, called opcodes, that can be issued by the bus master to the fm25h20. they are listed in table 1 . these opcodes control the functions performed by the memory. wren - set write enable latch the fm25h20 will power up with writes disabled. the wren command must be issued before any write operation. sending the wren opcode allows the user to issue subsequent opcodes for write operations. these incl ude writing the status register (wrsr) and writing the memory (write). sending the wren opcode causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of t he latch. wel = ?1? indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit ? only the wren opcode can set this bit. the wel bit will be aut omatically cleared on the rising edge of cs following a wrdi, a wrsr, or a write operation. this prevents further writes to t he status register or the f-ram array without another wren command. figure 7 illustrates the wren command bus configuration. wrdi - reset write enable latch the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel is equal to ?0?. figure 8 illustrates the wrdi command bus configuration. figure 5. spi mode 0 figure 6. spi mode 3 table 1. opcode commands name description opcode wren set write enable latch 0000 0110b wrdi reset write enable latch 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b write write memory data 0000 0010b sleep enter sleep mode 1011 1001b lsb msb 76543210 cs sck si 01 2 3 4 5 67 cs sck si 765432 10 lsb msb 01 2 3 4 5 67 figure 7. wren bus configuration figure 8. wrdi bus configuration 0 0 0 0 0 1 1 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 00 1 not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 7 of 22 status register and write protection the write protection features of the fm25h20 are multi-tiered and are enabled through the status register. the status register is organized as follows. (the default value shipped from the factory for bit 0, wel, bp0, bp1, bits 4?5, wpen is ?0?, and for bit 6 is ?1?.) bits 0 and 4-5 are fixed at ?0? and bit 6 is fixed at ?1?; none of these bits can be modified. note that bit 0 ("ready or write in progress? bit in serial flash and eeprom) is unnecessary, as the f-ram writes in real-time and is never busy, so it reads out as a ?0?. an exception to this is when the device is waking up from sleep mode, which is described in sleep mode on page 10 . the bp1 and bp0 control the software writ e-protection features and are nonvolatile bits. the wel flag indicates the state of the write enable latch. attempting to dire ctly write the wel bit in the status register has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify portions of me mory that are write- protected as shown in ta b l e 4 . the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memo ry from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the write protect enable bit (wpen) in the status register controls the effect of the hardware write protect (wp ) pin. when the wpen bit is set to '0', the status of the wp pin is ignored. when the wpen bit is set to '1', a low on the wp pin inhibits a write to the status register. thus the status register is write-protected only when wpen = '1' and wp = '0'. ta b l e 5 summarizes the write protection conditions. table 2. status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen (0) x (1) x (0) x (0) bp1 (0) bp0 (0) wel (0) x (0) table 3. status register bit definition bit definition description bit 0 don?t care this bit is non-writable and always returns ?0? upon read. bit 1 (wel) write enable wel indicates if the device is writ e enabled. this bit defaults to ?0? (disabled) on power-up. wel = '1' --> write enabled wel = '0' --> write disabled bit 2 (bp0) block protect bit ?0? used for block protection. for details, see table 4 on page 7 . bit 3 (bp1) block protect bit ?1? used for block protection. for details, see table 4 on page 7 . bit 4-5 don?t care these bits are non-writable and always return ?0? upon read. bit 6 don?t care this bit is non-writable and always returns ?1? upon read. bit 7 (wpen) write protect enable bit used to ena ble the function of write protect pin (wp ). for details, see table 5 on page 7 . table 4. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 30000h to 3ffffh (upper 1/4) 1 0 20000h to 3ffffh (upper 1/2) 1 1 00000h to 3ffffh (all) table 5. write protection wel wpen wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 8 of 22 rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading the status register provides information about the current state of the write-protection features. fo llowing the rdsr opcode, the fm25h20 will return one byte with the contents of the status register. wrsr - write status register the wrsr command allows the spi bus master to write into the status register and change the write protect configuration by setting the wpen, bp0 and bp1 bits as required. before issuing a wrsr command, the wp pin must be high or inactive. note that on the fm25h20, wp only prevents writing to the status register, not the memory array. before sending the wrsr command, the user must send a wren command to enable writes. executing a wrsr command is a write operation and therefore, clears the write enable latch. memory operation the spi interface, which is capable of a high clock frequency, highlights the fast write capability of the f-ram technology. unlike serial flash and eeprom s, the fm25h20 can perform sequential writes at bus speed. no page register is needed and any number of sequential wr ites may be performed. write operation all writes to the memory begin with a wren opcode with cs being asserted and deasserted. the next opcode is write. the write opcode is followed by a three-byte address containing the 18-bit address (a17-a0) of the first data byte to be written into the memory. the upper six bits of the three-byte address are ignored. subsequent bytes are data bytes, which are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and keeps cs low. if the last address of 3ffffh is re ached, the counter will roll over to 00000h. data is written msb first. the rising edge of cs terminates a write operation. a write operation is shown in figure 11 . note when a burst write reaches a protected block address, the automatic address increment stops and all the subsequent data bytes received for write will be ignored by the device. eeproms use page buffers to in crease their write throughput. this compensates for the technology's inherently slow write operations. f-ram memories do not have page buffers because each byte is written to the f-ram array immediately after it is clocked in (after the eighth clock). this allows any number of bytes to be written without page buffer delays. note if the power is lost in the mi ddle of the write operation, only the last completed byte will be written. figure 9. rdsr bus configuration figure 10. wrsr bus configuration (wren not shown) cs sck so 01234567 si 000001 0 0 1 hi-z 012345 67 lsb d0d1d2d3d4d5d6 msb d7 opcode data cs sck so 0123 4567 si 00 00000 1 msb lsb d2d3 d7 hi-z 012345 67 opcode data xx xx x not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 9 of 22 read operation after the falling edge of cs , the bus master can issue a read opcode. following the read command is a three-byte address containing the 18-bit address (a17-a0) of the first byte of the read operation. the upper six bits of the address are ignored. after the opcode and address are issued, the device drives out the read data on the next eight clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and cs is low. if the last address of 3fff fh is reached, the counter will roll over to 00000h. data is read msb first. the rising edge of cs terminates a read operation and tristates the so pin. a read operation is shown in figure 12 . figure 11. memory write (wren not shown) operation figure 12. memory read operation ~ ~ cs sck so 01234 5 6 70 7 65432 1 2021222301234567 msb lsb data d0d1d2d3d4d5d6d7 si ~ ~ opcode 0000001 x x x x x a17 0 x a16 a3 a1a2 a0 18-bit address msb lsb hi-z ~ ~ cs sck so 01 23456 70 7 65432 1 20212223012345 6 7 msb lsb data si ~ ~ opcode 0000001 x x x x x a17 1 x a16 a3 a1a2 a0 18-bit address msb lsb d0d1d2d3d4d5d6d7 hi-z not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 10 of 22 hold pin operation the hold pin can be used to interrupt a serial operation without aborting it. if the bus master pulls the hold pin low while sck is low, the current operation will pause. taking the hold pin high while sck is low will resume an operation. the transitions of hold must occur while sck is low, but the sck and cs pin can toggle during a hold state. sleep mode a low-power sleep mode is implemented on the fm25v20 device. the device will enter the low-power state when the sleep opcode b9h is clocked in and a rising edge of cs is applied. when in sleep mode, the sck and si pins are ignored and so will be hi-z, but the device continues to monitor the cs pin. on the next falling edge of cs , the device will return to normal operation within t rec time. the so pin remains in a hi-z state during the wakeup period. the device does not necessarily respond to an opcode within the wakeup period. to start the wakeup procedure, the controller may send a ?dummy? read, for example, and wait the remaining t rec time. figure 13. hold operation [2] cs sck hold so ~ ~ ~ ~ si valid in valid in ~ ~ ~ ~ ~ ~ figure 14. sleep mode operation cs sck si so hi-z 0 enters sleep mode valid in t su t rec recovers from sleep mode 10111 00 1 1 2 3 4 5 6 7 note 2. figure shows hold operation for input mode and output mode. not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 11 of 22 endurance the fm25h20 devices are capable of being accessed at least 10 14 times, reads or writes. an f-ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f-ram architec ture is based on an array of rows and columns of 32k rows of 64-bits each. the entire row is internally accessed each time a byte in that row is read or written. all 8 bytes in the row are counted separately for each access in an endurance calculation. ta b l e 7 shows endurance calculations for a 256-byte repeating loop, which includes an opcode, a starting address (3 bytes), and a sequential 256-byte data stream. this causes each byte to experience eight endurance cycle through the loop. f-ram read and write endurance is virtually unlimited even at a 40-mhz clock rate. table 6. time to reach endurance limit for repeating 256-byte loop sck freq (mhz) endurance cycles/sec endurance cycles/year years to reach limit 40 153,848 4.85 10 12 20.6 20 76,924 2.43 10 12 41.2 10 38,462 1.21 10 12 82.4 5 19,231 6.06 10 11 164.8 not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 12 of 22 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +125 ?c maximum junction temperature ................................... 95 ?c supply voltage on v dd relative to v ss .........?1.0 v to +4.5 v input voltage ........... ?1.0 v to +4.5 v and v in < v dd + 1.0 v dc voltage applied to outputs in high-z state .................................... ?0.5 v to v dd + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ............ ..... ?2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount lead soldering temperature (3 seconds) ........ ............................ ..... +260 ?c dc output current (1 output at a time, 1s duration) .... 15 ma electrostatic discharge voltage human body model (jedec std jesd22-a114-b) .............. 2 kv charged device model (jedec std jesd22-c101-a) .......... 1 kv machine model (jedec std jesd22-a115-a) ...................... 200 v latch-up current ...................................................... > 50 ma operating range range ambient temperature (t a ) v dd industrial ?40 ? c to +85 ? c 2.7 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [3] max unit v dd power supply 2.7 3.3 3.6 v i dd v dd supply current sck toggling between v dd ? 0.2 v and v ss , other inputs v ss or v dd ? 0.2 v. so = open f sck = 1 mhz; ??1m a f sck = 40 mhz; ? ? 10 ma i sb v dd standby current cs = v dd . all other inputs v ss or v dd . t a = 25 ? c?80150 ? a t a = 85 ? c? ?270 ? a i zz sleep mode current cs = v dd . all other inputs v ss or v dd . t a = 25 ? c?35 ? a t a = 85 ? c??8 ? a i li input leakage current v ss < v in < v dd ??1 ? a i lo output leakage current v ss < v out < v dd ??1 ? a v ih input high voltage 0.7 v dd ?v dd + 0.5 v v il input low voltage ? 0.4 ? 0.3 v dd v v oh output high voltage i oh = ?100 ? av dd ? 0.2 ? ? v v ol output low voltage i ol = 1.6 ma ? ? 0.4 v note 3. typical values are at 25 c, v dd = v dd (typ). not 100% tested. not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 13 of 22 ac test conditions input pulse levels .................................10% and 90% of v dd input rise and fall times ...................................................3 ns input and output timing reference levels ................0.5 v dd output load capacitance .............................................. 30 pf data retention and endurance parameter description test condition min max unit t dr data retention t a = 85 ? c 10 ? years t a = 75 ?c3 8 ? t a = 65 ?c 151 ? nv c endurance over operating temperature 10 14 ? cycles capacitance parameter [4] description test conditions max unit c o output pin capacitance (so) t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) 8 pf c i input pin capacitance 6pf thermal resistance parameter description test conditions 8-pin soic 8-pin tdfn unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 112 16 ?c/w ? jc thermal resistance (junction to case) 37 10 ?c/w note 4. this parameter is characte rized but not 100% tested. not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 14 of 22 ac switching characteristics over the operating range parameters [5] description v dd = 2.7 v to 3.6 v unit cypress parameter alt. parameter min max f sck ? sck clock frequency 0 40 mhz t ch ? clock high time 11 ? ns t cl ? clock low time 11 ? ns t csu t css chip select setup 10 ? ns t csh t csh chip select hold 10 ? ns t od [6, 7] t hzcs output disable time ? 12 ns t odv t co output data valid time ? 9 ns t oh ? output hold time 0 ? ns t d ? deselect time 40 ? ns t r [8, 9] ? data in rise time ? 50 ns t f [8, 9] ? data in fall time ? 50 ns t su t sd data setup time 5 ? ns t h t hd data hold time 5 ? ns t hs t sh hold setup time 10 ? ns t hh t hh hold hold time 10 ? ns t hz [6, 7] t hhz hold low to hi-z ? 20 ns t lz [7] t hlz hold high to data active ? 20 ns notes 5. test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 10% to 90% of v dd , and output loading of the specified i ol /i oh and 30 pf load capacitance shown in ac test conditions on page 13 . 6. t od and t hz are specified with a load capacitance of 5 pf. transiti on is measured when the outputs enter a high impedance state 7. this parameter is characterized but not 100% tested. 8. rise and fall times measured between 10% and 90% of waveform. 9. these parameters are guaranteed by design and are not tested. not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 15 of 22 figure 15. synchronous data timing (mode 0) figure 16. hold timing hi-z valid in hi-z cs sck si so t cl t ch t csu t su t h t odv t oh t d t csh t od valid in valid in cs sck hold so t hs t hz t lz t hh t hs t hh ~ ~ ~ ~ si t su valid in valid in ~ ~ ~ ~ ~ ~ not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 16 of 22 power cycle timing over the operating range parameter description min max unit t pu power-up v dd (min) to first access (cs low) 1 ? ms t pd last access (cs high) to power-down (v dd (min)) 0 ? s t vr [10] v dd power-up ramp rate 50 ? s/v t vf [10] v dd power-down ramp rate 100 ? s/v t rec [11] recovery time from sleep mode ? 450 s figure 17. power cycle timing cs ~ ~ ~ ~ t pu t vr t vf v dd v dd(min) t pd v dd(min) notes 10. slope measured at any point on the v dd waveform. 11. guaranteed by design. refer to figure 14 for sleep mode recovery timing. not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 17 of 22 ordering code definitions ordering information ordering code package diagram package type operating range FM25H20-G 001-85261 8-pin soic industrial FM25H20-Gtr 001-85261 8-pin soic fm25h20-dg 001-85579 8-pin tdfn fm25h20-dgtr 001-85579 8-pin tdfn all these parts are pb-free. contact your local cypre ss sales representative for availability of these parts. option: blank = standard; tr = tape and reel package type: g = 8-pin soic; dg = 8-pin tdfn density: 20 = 2-mbit voltage: h = 2.7 v to 3.6 v spi f-ram cypress 25 fm h 20 - dg tr not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 18 of 22 package diagrams figure 18. 8-pin soic (208 mils) package outline, 001-85261 001-85261 ** not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 19 of 22 figure 19. 8-pin dfn (5 mm 6 mm 0.60 mm) package outline, 001-85579 package diagrams (continued) 001-85579 ** not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 20 of 22 acronyms document conventions units of measure acronym description cpha clock phase cpol clock polarity eeprom electrically erasable programmable read-only memory eia electronic industries alliance f-ram ferroelectric random access memory i/o input/output jedec joint electron devices engineering council jesd jedec standards lsb least significant bit msb most significant bit rohs restriction of hazardous substances spi serial peripheral interface soic small outline integrated circuit tdfn thin dual flat no-lead symbol unit of measure c degree celsius hz hertz khz kilohertz k? kilohm mbit megabit mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt not recommended for new designs
preliminary fm25h20 document number: 001-85935 rev. *d page 21 of 22 document history page document title: fm25h20, 2-mbit (256 k 8) serial (spi) f-ram document number: 001-85935 rev. ecn no. orig. of change submission date description of change ** 3902952 gvch 02/25/13 new spec *a 3924836 gvch 03/07/13 move datasheet to external web *b 3994285 gvch 05/14/2013 added appendix a - errata for fm25h20 *c 4045438 gvch 06/30/2013 all errata items are fixed and the errata is removed. *d 4226252 gvch 01/24/2014 converted to cypress standard format updated pinouts - updated figure 2 (added exposed pad details) updated pin definitions - added exposed pad details. updated maximum ratings table - removed moisture sensitivity level (msl) - added junction temperature and latch up current updated data retention and endurance table - added data retention value at 65 ? c and 75 ? c temperature added thermal resistance table removed package marking scheme (top mark) updated figure 19 removed ramtron revision history completing sunset review added watermark as ?not recommended for new designs?. not recommended for new designs
document number: 001-85935 rev. *d revised january 24, 2014 page 22 of 22 all products and company names mentioned in this document may be the trademarks of their respective holders. preliminary fm25h20 ? cypress semiconductor corporation, 2013-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representative s, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support not recommended for new designs

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